Delta-sigma conversion is an analog-digital conversion technique based on over sampling and formatting of quantification noise. An example of a delta-sigma analog-digital converter according to prior art is illustrated on FIG. 1. This converter is formed from a delta-sigma modulator 10 followed by a digital processing stage 30. The digital processing stage 30 may include a digital filter 32 and an under sampling stage 34.
The delta-sigma modulator 10 can reject noise due to quantification of the converter input signal to frequencies located outside the required pass band. In this example, the order of the delta-sigma modulator 10 is 1 and includes a stage provided with a summation node 11, an integrator 12, and a quantifier 16 at the output from the integrator 12. The quantifier 16 is controlled by a sampling clock signal with frequency fs, and may be in the form of a blocking sampler followed by an analog-digital converter comprising one or several comparators.
The quantifier 16 may possibly be a low resolution quantifier formed from a single comparator. The modulator also includes at least one return or feedback digital-analog converter that can switch between two reference voltages, for example between a reference voltage −Vref and another reference voltage +Vref.
Depending on the order of the delta-sigma modulator, the modulator may be provided with several adjacent stages and may include a plurality of integrators. The integrators used in a delta-sigma modulator are usually pure integrators. A pure integrator means an element for which the output is proportional to the integral of the input signal, and for which the Laplace transform transfer function is equal to 1/s.
In a case in which the modulator is order N (where N is an integer≧2) and includes a plurality of pure integrators, implementation of the first integrator, in other words the integrator closest to the modulator input, is the most critical in that this first integrator needs to support the most severe constraints in terms of noise and linearity among the plurality of pure integrators. Constraints for manufacturing the first integrator are greater when the required pass bands are wider and require high operating speeds. Integrators in a delta-sigma modulator may be of a discrete time type, and for example, may be made using switched capacitors, or in one variation, continuous time type integrators may be used. Delta-sigma modulators fitted with continuous time integrators are usually capable of operating at higher speeds than discrete time modulators.
A pure continuous time integrator is usually made using one of the two methods described below that are illustrated with reference to FIGS. 2 and 3, respectively.
FIG. 2 shows an illustration of a first embodiment of the pure integrator 12 of the modulator described above with reference to FIG. 1. This integrator is said to be a transconductance integrator and comprises means 21 capable of forming a transconductance with value Gm and designed to convert an integrator input voltage V1 into a current I=Gm*V1. The current I is integrated through a capacitor 23 at the output from the transconductance. A signal V2 proportional to the integral of the input signal V1 is produced at the output of the integrator. Such a structure has the advantage that it operates in an open loop and is therefore fast.
A return signal Idac delivered by the digital-analog converter 14 to the integrator 12 does not pass through any active element, and it is integrated into the terminals of the capacitor 23. However, the performances of the integrator is related to the performance of the transconductance 21. This transconductance is difficult to implement and creates problems particularly with sensitivity to noise and a lack of linearity, when the delta-sigma modulator is made with a low power supply voltage, for example, on the order of 1.2 volts.
A second embodiment of the integrator 12 is illustrated on FIG. 3. In this second embodiment, the integrator is said to be an operational amplifier integrator and includes a resistance 25 with value R located at the input to the operational amplifier 27. The resistance can convert an input voltage V1 to the integrator into a current integrated at the terminals of a capacitor 26 with capacitance C, connected between the input and output terminals of the operational amplifier 27. Such an integrator structure operates in a closed loop and has the advantage of being very linear. On the other hand, its operating speed is limited by performances of the operational amplifier 27, and particularly by the product of the gain and the band of this amplifier 27. With such an integrator, the digital-analog converter 14 outputs a return signal Idac to a capacitor terminal 26 and at the input of the operational amplifier 27.
An architecture of an order N delta-sigma modulator (where N is a positive integer) according to the prior art, represented as an equivalent Laplace transform model, is illustrated on FIG. 4. Such a delta-sigma modulator comprises n pure transconductance type integrators 201, . . . , 20n (as described previously with reference to FIG. 2) or operational amplifier type integrators (as described previously with reference to FIG. 3), and with an equivalent transfer function of 1/s. The order N delta-sigma modulator is also provided with 1 to n feedback or return digital-analog converters 141, . . . , 14n, with gains of b1, b2, b3, . . . bn respectively. The delta-sigma modulator is also provided with a quantifier (represented by a block reference 34 on FIG. 4)